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O que (quem) é X86 memory models - definição
X86 memory models
SET OF MEMORY MODELS OF THE X86 CPU
Near pointer; Huge pointer; C memory model; Intel Memory Model; Intel memory model
In computing, Intel Memory Model refers to a set of six different memory models of the x86 CPU operating in real mode which control how the segment registers are used and the default size of pointers.
X86 memory segmentation
THE IMPLEMENTATION OF MEMORY SEGMENTATION ON THE X86 ARCHITECTURE
Segment registers; FS and GS; FS/GS; Segment selector; X86 memory segment; Segmented address; Paragraph (computing); Paragraph (Intel); Segment:offset notation (x86); Segment:offset addressing (x86); Segment:offset addressing scheme (x86); Segment:offset (x86); Segment:offset memory addressing (x86); X86 segment:offset addressing; X86 segment:offset addressing scheme; X86 segment:offset; X86 segment:offset memory addressing
x86 memory segmentation refers to the implementation of memory segmentation in the Intel x86 computer instruction set architecture. Segmentation was introduced on the Intel 8086 in 1978 as a way to allow programs to address more than 64 KB (65,536 bytes) of memory.
X86
![[[Am386]], released by AMD in 1991](https://commons.wikimedia.org/wiki/Special:FilePath/Am386SXL-25cropped.jpg?width=200 "[[Am386]], released by AMD in 1991")
![Alpha]], and others), and 32-bit x86 (green on the diagram), even though Intel initially tried unsuccessfully to replace x86 with a new incompatible 64-bit architecture in the [[Itanium]] processor. The main non-x86 architecture which is still used, as of 2014, in supercomputing clusters is the [[Power ISA]] used by [[IBM Power microprocessors]] (blue with diamond tiling in the diagram), with SPARC as a distant second.](https://commons.wikimedia.org/wiki/Special:FilePath/Processor families in TOP500 supercomputers.svg?width=200 "Alpha]], and others), and 32-bit x86 (green on the diagram), even though Intel initially tried unsuccessfully to replace x86 with a new incompatible 64-bit architecture in the [[Itanium]] processor. The main non-x86 architecture which is still used, as of 2014, in supercomputing clusters is the [[Power ISA]] used by [[IBM Power microprocessors]] (blue with diamond tiling in the diagram), with SPARC as a distant second.")
TYPE OF INSTRUCTION SET ARCHITECTURE
80x86; Intel 80x86; 8x86; 80786; X86-16; Intel 80786; Intel x86; IA 32; X-86; X86 pro; X86-based CPU; X86-based system; X86 based; X86 clone; X86 compatible; Intel-based CPU; Intel-based cpu; Intel 16; Intel compatible; Intel-compatible; Intel clone; X86 architecture; Accumulator eXtended; AL register; AH register; AX register; BX register; CX register; DX register; BH register; BL register; CL register; CH register; DH register; DL register; Base pointer; DS register; ES register; SS register; DI register; SI register; FS register; GS register; X86 registers; BP register; EAX register; EBX register; ECX register; EDX register; ESP register; EBP register; ESI register; EDI register; EIP register; RIP register; RFLAGS register; RAX register; RBX register; RCX register; RDX register; RSI register; RDI register; RBP register; RSP register; GDTR register; LDTR register; IDTR register; TR register; IP register; Source index; Destination index; IAPX 86 series; X86 microprocessor
and so cannot be subject to patent claims. The pre-586 subset of the x86 architecture is therefore fully open.
